The present invention relates to a flash memory device, and more particularly, to a flash memory device capable of verifying whether selected data bits have program data values, and a programming method of the flash memory device.
Generally, a flash memory device is a kind of electrically erasable programmable read only memory (EEPROM), in which multiple memory regions are simultaneously erased or programmed in one program operation. Because EEPROM can be electrically erased and programmed, it is extensively employed in system programming or in auxiliary devices, which require continuous updating. Also, because a flash EEPROM (hereinafter, referred to as flash memory) has a higher degree of integration than a typical EEPROM, it is particularly useful in high capacity auxiliary memory devices.
A flash memory device may include a NAND flash memory or a NOR flash memory, according to the structure of the corresponding logic gate used in each storage device. The NAND flash memory device provides a higher degree of integration, as compared to the NOR flash memory device.
FIG. 1 is a block diagram of a typical NAND flash memory device.
Referring to FIG. 1, the NAND flash memory device 10 includes a memory cell array 20, a row selection circuit (X-SEL) 40 and a page buffer circuit 60. The memory cell array 20 includes multiple cell strings (i.e., NAND strings) 21 connected to bit lines BL0 to BLm−1, respectively. Each cell string or column includes a string selection transistor SST as a first selection transistor, a ground selection transistor GST as a second selection transistor, and multiple flash EEPROM cells or memory cells MC0 to MCn−1 connected in series between the selection transistors SST and GST.
The string selection transistor SST in each column includes a drain connected to the corresponding bit line and a gate connected to a string selection line SSL. The ground selection transistor GST includes a source connected to a common source line CSL and a gate connected to a ground selection line GSL. The memory cells MC0 to MCn−1 are connected in series between the source of the string selection transistor SST and the drain of the ground selection transistor GST. The cells in each cell string include floating gate transistors. Control gates of the floating gate transistors are connected to corresponding word lines WL0 to WLn−1, respectively.
The string selection line SSL, the word lines WL0 to WLn−1, and the ground selection line GSL are electrically connected to the row selection circuit 40. The row selection circuit 40 selects one of the word lines WL0 to WLn−1 according to row address information, and supplies word line voltages to the selected word line and unselected word lines according to each operating mode. For example, the row selection circuit 40 supplies a program voltage to a word line selected during a program operating mode, and passes voltages to unselected word lines. The row selection circuit 40 supplies a ground voltage GND to a word line selected during a read operating mode. The program voltage, the pass voltage and the read voltage are higher than a power supply voltage.
Bit lines BL0 to BLm−1 in the memory cell array 20 are electrically connected to the page buffer circuit 60. The page buffer circuit 60 detects data from the memory cells of the word line selected through the bit lines BL0 to BLm−1 during a read/verify operating mode. It is determined whether the memory cell is a programmed cell or an erased cell through a detect operation of the page buffer circuit 60. Additionally, the page buffer circuit 60 supplies a power supply voltage (i.e., a program-inhibited voltage) or a ground voltage (i.e., a program voltage) to the bit lines BL0 to BLm−1 during a program operating mode, according to data to be programmed. The page buffer circuit 60 may include page buffers corresponding to bit lines BL0 to BLm−1, respectively. Alternatively, each page buffer may be configured to share a pair of bit lines.
The memory cell of the NAND flash memory 10 is erased and programmed through a Fowler-Nordheim tunneling current. Erasing and programming methods of a NAND flash memory are disclosed, for example, in U.S. Pat. No. 5,473,563 to Suh et al., entitled “Nonvolatile Semiconductor Memory,” and in U.S. Pat. No. 5,696,717 to Koh, entitled “Nonvolatile Integrated Circuit Memory Devices Having Adjustable Erase/Program Threshold Voltage Verification Capability.”
Additionally, the flash memory device is programmed using incremental step pulse programming (ISPP) in order to accurately control threshold voltage distributions of their memory cells. An exemplary programming method of the flash memory device using the ISPP method is disclosed in U.S. Pat. No. 6,266,270, to Nobukata, entitled “Non-Volatile Semiconductor Memory and Programming Method of the Same.” One example of a circuit generating a program voltage according to the ISPP method is disclosed in U.S. Pat. No. 5,642,309, to Kim, et al., entitled “Auto-Program Circuit in a Nonvolatile Semiconductor Memory Device,” and in Korean Patent No. 2002-39744 entitled “Flash Memory Device Capable of Preventing Program Disturb and Method of Programming the Same.”
During a program operation of the flash memory device 10, data to be programmed are sequentially delivered to the page buffer circuit 60 by a byte or word unit. When the data to be programmed, e.g., one page, are loaded into the page buffer circuit 60, the data in the page buffer circuit 60 are simultaneously programmed into the memory cell array 20 (e.g., memory cells of a selected page), according to a program command.
To program a flash memory device using the ISSP method, a cycle during which data are programmed (hereinafter, referred to as a “program cycle”) includes multiple program loops (i.e., “ISSP loops”). Additionally, each ISSP loop is divided into a program loop and a program verify loop. During the program loop, memory cells are programmed under a bias condition according to a typical method. During the program verify loop, it is determined whether memory cells are programmed to a required threshold voltage. Until all the memory cells are programmed within the predetermined number of times, the program loops are repeatedly performed. The program verify operation is essentially the same in the read operation except that read data are not output.
A verify method for determining whether memory cells are programmed to a required threshold voltage includes a wired-OR type method and a column scan type method (also, referred to as a “Y-scan method”). An exemplary memory device using a column scan method is disclosed in U.S. Pat. No. 6,282,121, to Cho, et al., entitled “Flash Memory Device with Program Status Detection Circuitry and the Method Thereof.”
The typical flash memory device 10 further includes a column selection circuit (not shown) and a pass/fail check circuit (not shown). After a program operation, when verifying a program state using the Y-scan method, the column selection circuit selects page buffers of the page buffer circuit 60 by predetermined unit in response to a column address. Data bits of the selected page buffers are transferred to the pass/fail check circuit through the column selection circuit. The pass/fail check circuit determines whether all inputted data bits have program data values. When the memory cells are normally programmed, the data bits have program data values, referred to as “program pass.” In this case, the column address is incrementally increased (increased by one column address), and the incremented column address is provided into the column selection circuit. Following data values are selected by the counted-up column address.
When the memory cells are programmed abnormally, data bits of the memory cells do not have program data values, referred to as “program fail.” In this case, the flash memory device terminates the Y-scan operation, and increases a program voltage by a predetermined level through the ISSP method after storing the column address. Then, the flash memory device performs the programming operation again. After the repeated programming operation, the flash memory device again performs the Y-scan operation starting from the stored column address. This program verify operation repeats until the failed cells are normally programmed, and also until all the memory cells of the selected page are selected, i.e., the last column address is generated.
FIG. 2 is a graph illustrating changes of a threshold voltage distribution of a conventional flash memory device programmed according to an ISPP method.
Referring to FIG. 2, the typical flash memory device performs program operations according to the ISPP method in order to raise a threshold voltage of a cell in an erased state higher than a verify voltage with respect to a read voltage. When using the ISPP method, threshold voltage distribution of the cell overlaps that of the normally-programmed cell. When it is determined that all of the cells to be programmed are normally programmed during a program verify operation, the flash memory device finishes a verify operation and terminates a program. The threshold voltage distribution of the normally-programmed cells is higher than the verify voltage, as illustrated in FIG. 2.
However, there may be some cells that do not have a voltage higher than the verify voltage during the program operation. These cells are not normally programmed and may be referred to as “slow cells” or “fail bit cells.” As illustrated in FIG. 2, the threshold voltage distribution of the slow cell (hereinafter, referred to as the “fail bit cell”) is lower than the verify voltage.
When performing a verify operation through the Y-scan method, the flash memory device terminates the Y-scan operation and stores a column address when there is a fail bit cell. Then, the flash memory device raises the program voltage by a predetermined level and performs the program operation again. After performing the program operation, the flash memory device performs the Y-scan operation starting from the stored column address. This operation repeats until all fail bit cells are normally programmed, and the program voltage incrementally increases each time the operation repeats. As a result, the number of program loops increases, and a program time for the flash memory device increases. Additionally, an unnecessary program voltage is applied to the normally-programmed cells due to the repeating program loops, causing unnecessary stress to the normally-programmed cells. Due to this stress, the threshold voltage distribution of the normally-programmed cells may shift in the direction of the arrow illustrated in FIG. 2, resulting in decreased reliability of the programmed cell.
Consequently, program performance deteriorates because the flash memory device repeatedly performs program loops in order to normally program a few fail bit cells.